<?xml version="1.0" encoding="UTF-8" standalone="yes"?><oembed><version><![CDATA[1.0]]></version><provider_name><![CDATA[Atmel | Bits &amp; Pieces]]></provider_name><provider_url><![CDATA[https://atmelcorporation.wordpress.com]]></provider_url><author_name><![CDATA[tomvanvu]]></author_name><author_url><![CDATA[https://atmelcorporation.wordpress.com/author/tomvanvu/]]></author_url><title><![CDATA[On-chip DMA and low-latency access SRAM&nbsp;architecture]]></title><type><![CDATA[photo]]></type><url><![CDATA[https://atmelcorporation.files.wordpress.com/2015/06/on-chip-dma-and-low-latency-access-sram-architecture1.jpg?fit=440%2C330]]></url><width><![CDATA[440]]></width><height><![CDATA[264]]></height></oembed>